Jose Raul Garcia Ordaz
Publication record assembled from the DBLP archive of ranked conferences.
Papers indexed
2
Venues
1
Active years
2017–2017
Best venue rank
B
Where they publish
Papers
2 indexed papers, newest first.
| Year | Venue | Title | Authors |
|---|---|---|---|
| 2017 | FPL | Making a case for an ARM Cortex-A9 CPU interlay replacing the NEON SIMD unit. | Jose Raul Garcia Ordaz, Dirk Koch |
| 2017 | FPL | A security library for FPGA interlays. | Anuj Vaishnav, Jose Raul Garcia Ordaz, Dirk Koch |