Juan Nez
Publication record assembled from the DBLP archive of ranked conferences.
Papers indexed
9
Venues
3
Active years
2006–2020
Best venue rank
C
Where they publish
Papers
9 indexed papers, newest first.
| Year | Venue | Title | Authors |
|---|---|---|---|
| 2020 | ISCAS | An Approach to the Device-Circuit Co-Design of HyperFET Circuits. | Manuel Jimnez Travs, Juan Nez, Maria Jos Avedillo |
| 2017 | ISCAS | Exploring logic architectures suitable for TFETs devices. | Juan Nez, Maria J. Avedillo |
| 2013 | DSD | Novel Dynamic Gate Topology for Superpipelines in DSM Technologies. | Juan Nez, Maria J. Avedillo, Jos M. Quintana |
| 2010 | CASC | Computing Matrix Representations of Filiform Lie Algebras. | Manuel Ceballos, Juan Nez, ngel F. Tenorio |
| 2010 | DSD | Evaluation of RTD-CMOS Logic Gates. | Juan Nez, Maria J. Avedillo, Jos M. Quintana |
| 2010 | ISCAS | Single phase MOS-NDR mobile networks. | Juan Nez, Maria J. Avedillo, Jos M. Quintana |
| 2009 | ISCAS | Fast and Area Efficient Multi-input Muller C-Element based on MOS-NDR. | Juan Nez, Jos M. Quintana, Maria J. Avedillo |
| 2008 | ISCAS | Limits to a correct operation in RTD-based ternary inverters. | Juan Nez, Jos M. Quintana, Maria J. Avedillo |
| 2006 | DSD | Design Guides for a Correct DC Operation in RTD-based Threshold Gates. | Jos M. Quintana, Maria J. Avedillo, Juan Nez |