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Julian Oppermann

Publication record assembled from the DBLP archive of ranked conferences.

Papers indexed

17

Venues

11

Active years

2014–2024

Best venue rank

A*

Where they publish

Papers

17 indexed papers, newest first.

YearVenueTitleAuthors
2024ASPLOSLongnail: High-Level Synthesis of Portable Custom Instruction Set Extensions for RISC-V Processors from Descriptions in the Open-Source CoreDSL Language.Julian Oppermann, Brindusa Mihaela Damian-Kosterhon, Florian Meisel, Tammo Mrmann, Eyck Jentzsch, Andreas Koch
2024CGOExperiences Building an MLIR-Based SYCL Compiler.Ettore Tiotto, Victor Perez, Whitney Tsang, Lukas Sommer, Julian Oppermann, Victor Lomller, Mehdi Goli, James Brodman
2024EuroParRuntime Instantiation of Kernels for Fast Fourier Transforms Using SYCL Specialization Constants.Victor Perez, Victor Lomller, Lukas Sommer, Julian Oppermann, Romain Biessy, Tadej Ciglaric, Mehdi Goli
2023SCAltis-SYCL: Migrating Altis Benchmarking Suite from CUDA to SYCL for GPUs and FPGAs.Christoph Weckert, Leonardo Solis-Vasquez, Julian Oppermann, Andreas Koch, Oliver Sinnen
2022DACSCAIE-V: an open-source SCAlable interface for ISA extensions for RISC-V processors.Mihaela Damian, Julian Oppermann, Christoph Spang, Andreas Koch
2022DATEThe Scale4Edge RISC-V Ecosystem.Wolfgang Ecker, Peer Adelt, Wolfgang Mller, Reinhold Heckmann, Milos Krstic, Vladimir Herdt, Rolf Drechsler, Gerhard Angst, Ralf Wimmer, Andreas Mauderer, Rafael Stahl, Karsten Emrich, Daniel Mueller-Gritschneder, Bernd Becker, Philipp Scholl, Eyck Jentzsch, Jan Schlamelcher, Kim Grttner, Paul Palomero Bernardo, Oliver Bringmann, Mihaela Damian, Julian Oppermann, Andreas Koch, Jrg Bormann, Johannes Partzsch, Christian Mayr, Wolfgang Kunz
2019CGOExtending LLVM for Lightweight SPMD Vectorization: Using SIMD and Vector Instructions Easily from Any Language.Robin Kruppe, Julian Oppermann, Lukas Sommer, Andreas Koch
2019EuroParDesign-Space Exploration with Multi-Objective Resource-Aware Modulo Scheduling.Julian Oppermann, Patrick Sittel, Martin Kumm, Melanie Reuter-Oppermann, Andreas Koch, Oliver Sinnen
2018CASESGeMS: a generator for modulo scheduling problems: work in progress.Julian Oppermann, Sebastian Vollbrecht, Melanie Reuter-Oppermann, Oliver Sinnen, Andreas Koch
2018EDBTNoFTL-KV: TacklingWrite-Amplification on KV-Stores with Native Storage Management.Tobias Vinon, Sergej Hardock, Christian Riegger, Julian Oppermann, Andreas Koch, Ilia Petrov
2018FPLDependence Graph Preprocessing for Faster Exact Modulo Scheduling in High-Level Synthesis.Julian Oppermann, Melanie Reuter-Oppermann, Lukas Sommer, Oliver Sinnen, Andreas Koch
2018FPLILP-Based Modulo Scheduling and Binding for Register Minimization.Patrick Sittel, Martin Kumm, Julian Oppermann, Konrad Mller, Peter Zipf, Andreas Koch
2018ICCDAutomatic Mapping of the Sum-Product Network Inference Problem to FPGA-Based Accelerators.Lukas Sommer, Julian Oppermann, Alejandro Molina, Carsten Binnig, Kristian Kersting, Andreas Koch
2016CASESILP-based modulo scheduling for high-level synthesis.Julian Oppermann, Andreas Koch, Melanie Reuter-Oppermann, Oliver Sinnen
2016UICDetecting Kernels Suitable for C-Based High-Level Hardware Synthesis.Julian Oppermann, Andreas Koch
2015FPLDomain-specific optimisation for the high-level synthesis of CellML-based simulation accelerators.Julian Oppermann, Andreas Koch, Ting Yu, Oliver Sinnen
2014FPLAutomatic high-level synthesis of multi-threaded hardware accelerators.Jens Huthmann, Julian Oppermann, Andreas Koch