Justin E. Harlow III
Publication record assembled from the DBLP archive of ranked conferences.
Papers indexed
6
Venues
6
Active years
1977–2006
Best venue rank
A*
Where they publish
Papers
6 indexed papers, newest first.
| Year | Venue | Title | Authors |
|---|---|---|---|
| 2006 | ISLPED | A novel approach for variation aware power minimization during gate sizing. | Venkataraman Mahalingam, N. Ranganathan, Justin E. Harlow III |
| 1999 | ISCAS | Mirror, mirror, on the wall...is the new release any different at all? [BDDs]. | Justin E. Harlow III, Franc Brglez |
| 1998 | DATE | Synthesis of Wiring Signature-Invariant Equivalence Class Circuit Mutants and Applications to Benchmarking. | Debabrata Ghosh, Nevin Kapur, Franc Brglez, Justin E. Harlow III |
| 1998 | FMCAD | Design of Experiments for Evaluation of BDD Packages Using Controlled Circuit Mutations. | Justin E. Harlow III, Franc Brglez |
| 1998 | ICCAD | Design of experiments in BDD variable ordering: lessons learned. | Justin E. Harlow III, Franc Brglez |
| 1977 | DAC | The open shop interactive mask design operation at harris semiconductor. | Justin E. Harlow III |