| 2026 | DATE | Late Breaking Results: Efficient Formal Verification of Highly Optimized MAC Units. | Jan Kleinekathfer, Lennart Weingarten, Kamalika Datta, Rolf Drechsler |
| 2026 | DDECS | Fan-In Aware Graph-Based Optimization for MAC-Based in-Memory Computing. | Fatemeh Shirinzadeh, Abhoy Kole, Kamalika Datta, Saeideh Shirinzadeh, Rolf Drechsler |
| 2025 | DATE | Late Breaking Results: Towards Efficient Formal Verification of Dot Product Architectures. | Lennart Weingarten, Kamalika Datta, Rolf Drechsler |
| 2025 | DDECS | Towards an Automated Debugging Approach for Fault Identification in Quantum Circuits. | Anton Maidl, Abhoy Kole, Kamalika Datta, Jannis Stoppe, Rolf Drechsler |
| 2025 | DSD | A Comprehensive Synthesis and Verification Approach for RRAM-Based Neuromorphic Computing. | Fatemeh Shirinzadeh, Abhoy Kole, Kamalika Datta, Saeideh Shirinzadeh, Rolf Drechsler |
| 2025 | FDL | ForMAt: Formal Verification of Scalable Multiply and Accumulate Units. | Lennart Weingarten, Kamalika Datta, Rolf Drechsler |
| 2024 | DATE | Dynamic Realization of Multiple Control Toffoli Gate. | Abhoy Kole, Arighna Deb, Kamalika Datta, Rolf Drechsler |
| 2024 | DATE | Complete and Efficient Verification for a RISC-V Processor Using Formal Verification. | Lennart Weingarten, Kamalika Datta, Abhoy Kole, Rolf Drechsler |
| 2024 | RC | Is Simulation the only Alternative for Effective Verification of Dynamic Quantum Circuits? | Liam Hurwitz, Kamalika Datta, Abhoy Kole, Rolf Drechsler |
| 2024 | VLSID | In-Memory SAT-Solver for Self-Verification of Programmable Memristive Architectures. | Fatemeh Shirinzadeh, Arighna Deb, Saeideh Shirinzadeh, Abhoy Kole, Kamalika Datta, Rolf Drechsler |
| 2023 | ASPDAC | Automated Equivalence Checking Method for Majority Based In-Memory Computing on ReRAM Crossbars. | Arighna Deb, Kamalika Datta, Muhammad Hassan, Saeideh Shirinzadeh, Rolf Drechsler |
| 2023 | DATE | Extending the Design Space of Dynamic Quantum Circuits for Toffoli based Network. | Abhoy Kole, Arighna Deb, Kamalika Datta, Rolf Drechsler |
| 2023 | RC | Improved Cost-Metric for Nearest Neighbor Mapping of Quantum Circuits to 2-Dimensional Hexagonal Architecture. | Kamalika Datta, Abhoy Kole, Indranil Sengupta, Rolf Drechsler |
| 2023 | RC | Exploiting the Benefits of Clean Ancilla Based Toffoli Gate Decomposition Across Architectures. | Abhoy Kole, Kamalika Datta, Philipp Niemann, Indranil Sengupta, Rolf Drechsler |
| 2022 | DSD | Unlocking Sneak Path Analysis in Memristor Based Logic Design Styles. | Kamalika Datta, Saeideh Shirinzadeh, Phrangboklang Lyngton Thangkhiew, Indranil Sengupta, Rolf Drechsler |
| 2022 | DSD | SAT-based Exact Synthesis of Ternary Reversible Circuits using a Functionally Complete Gate Library. | Abhoy Kole, Kamalika Datta, Indranil Sengupta, Rolf Drechsler |
| 2022 | GI | Mapping Quantum Circuits to 2-Dimensional Quantum Architectures. | Kamalika Datta, Abhoy Kole, Indranil Sengupta, Rolf Drechsler |
| 2020 | DATE | Fledge: Flexible Edge Platforms Enabled by In-memory Computing. | Kamalika Datta, Arko Dutt, Ahmed Zaky, Umesh Chand, Devendra Singh, Yida Li, Jackson Chun-Yang Huang, Aaron Thean, Mohamed M. Sabry Aly |
| 2020 | DATE | Quantifying the Benefits of Monolithic 3D Computing Systems Enabled by TFT and RRAM. | Abdallah M. Felfel, Kamalika Datta, Arko Dutt, Hasita Veluri, Ahmed Zaky, Aaron Voon-Yew Thean, Mohamed M. Sabry Aly |
| 2019 | ASPDAC | A staircase structure for scalable and efficient synthesis of memristor-aided logic. | Alwin Zulehner, Kamalika Datta, Indranil Sengupta, Robert Wille |
| 2019 | VLSID | Exploiting Negative Control Lines and Nearest Neighbor for Improved Comparator Design. | Tathagato Bose, Kamalika Datta, Indranil Sengupta |
| 2019 | VLSID | Design and Implementation of Threshold Logic Functions Using Memristors. | Yaswanth Krishna Yadav Danaboina, Pravanjan Samanta, Kamalika Datta, Indrajit Chakrabarti, Indranil Sengupta |
| 2019 | VLSID | Mapping of Boolean Logic Functions onto 3D Memristor Crossbar. | Naveen Murali G, Peddireddi Satya Vardhan, F. Lalchhandama, Kamalika Datta, Indranil Sengupta |
| 2017 | RC | Test Pattern Generation Effort Evaluation of Reversible Circuits. | Abhoy Kole, Robert Wille, Kamalika Datta, Indranil Sengupta |
| 2017 | RC | Design of Efficient Quantum Circuits Using Nearest Neighbor Constraint in 2D Architecture. | Leniency Marbaniang, Abhoy Kole, Kamalika Datta, Indranil Sengupta |
| 2017 | RC | Improved Decomposition of Multiple-Control Ternary Toffoli Gates Using Muthukrishnan-Stroud Quantum Gates. | P. Mercy Nesa Rani, Abhoy Kole, Kamalika Datta, Indranil Sengupta |
| 2017 | VLSID | Improved NCV Gate Realization of Arbitrary Size Toffoli Gates. | Abhoy Kole, Kamalika Datta |
| 2015 | RC | Towards a Cost Metric for Nearest Neighbor Constraints in Reversible Circuits. | Abhoy Kole, Kamalika Datta, Indranil Sengupta, Robert Wille |
| 2015 | VLSID | BDD-Based Synthesis for All-Optical Mach-Zehnder Interferometer Circuits. | Eleonora Schnborn, Kamalika Datta, Robert Wille, Indranil Sengupta, Hafizur Rahaman, Rolf Drechsler |
| 2014 | DDECS | Optimizing DD-based synthesis of reversible circuits using negative control lines. | Eleonora Schnborn, Kamalika Datta, Robert Wille, Indranil Sengupta, Hafizur Rahaman, Rolf Drechsler |
| 2014 | RC | RevVis: Visualization of Structures and Properties in Reversible Circuits. | Robert Wille, Jannis Stoppe, Eleonora Schnborn, Kamalika Datta, Rolf Drechsler |
| 2014 | VLSID | All Optical Reversible Multiplexer Design Using Mach-Zehnder Interferometer. | Kamalika Datta, Indranil Sengupta |
| 2013 | RC | Exploiting Negative Control Lines in the Optimization of Reversible Circuits. | Kamalika Datta, Gaurav Rathi, Robert Wille, Indranil Sengupta, Hafizur Rahaman, Rolf Drechsler |
| 2012 | VLSID | Synthesis of Reversible Circuits Using Heuristic Search Method. | Kamalika Datta, Gaurav Rathi, Indranil Sengupta, Hafizur Rahaman |