| 2017 | ISPASS | DARTS: Performance-counter driven sampling using binary translators. | Rajesh Kumar, Suchita Pati, Kanishka Lahiri |
| 2017 | ISPASS | Fast IPC estimation for performance projections using proxy suites and decision trees. | Kanishka Lahiri, Subhash Kunnoth |
| 2015 | HiPC | Characterizing Large Dataset GPU Compute Workloads Targeting Systems with Die-Stacked Memory. | Srividya Ramanathan, Gautam Hazari, Kanishka Lahiri, Francesco Spadini |
| 2007 | DAC | System-on-Chip Power Management Considering Leakage Power Variations. | Saumya Chandra, Kanishka Lahiri, Anand Raghunathan, Sujit Dey |
| 2007 | DAC | Accelerating System-on-Chip Power Analysis Using Hybrid Power Estimation. | Mohammad Ali Ghodrat, Kanishka Lahiri, Anand Raghunathan |
| 2007 | VLSID | Automatic Power Modeling of Infrastructure IP for System-on-Chip Power Analysis. | Nikhil Bansal, Kanishka Lahiri, Anand Raghunathan |
| 2007 | VLSID | Tutorial 5: SoC Communication Architectures: Technology, Current Practice, Research, and Trends. | Nikil D. Dutt, Kaustav Banerjee, Luca Benini, Kanishka Lahiri, Sudeep Pasricha |
| 2006 | DAC | Signature-based workload estimation for mobile 3D graphics. | Bren Mochocki, Kanishka Lahiri, Srihari Cadambi, Xiaobo Sharon Hu |
| 2006 | DATE | Power analysis of mobile 3D graphics. | Bren Mochocki, Kanishka Lahiri, Srihari Cadambi |
| 2006 | DATE | Integrated data relocation and bus reconfiguration for adaptive system-on-chip platforms. | Krishna Sekar, Kanishka Lahiri, Anand Raghunathan, Sujit Dey |
| 2006 | DATE | Adaptive data placement in an embedded multiprocessor thread library. | Phillip Stanley-Marbell, Kanishka Lahiri, Anand Raghunathan |
| 2006 | ISLPED | Considering process variations during system-level power analysis. | Saumya Chandra, Kanishka Lahiri, Anand Raghunathan, Sujit Dey |
| 2005 | DAC | FLEXBUS: a high-performance system-on-chip communication architecture with a dynamically configurable topology. | Krishna Sekar, Kanishka Lahiri, Anand Raghunathan, Sujit Dey |
| 2005 | VLSID | Power Monitors: A Framework for System-Level Power Estimation Using Heterogeneous Power Models. | Nikhil Bansal, Kanishka Lahiri, Anand Raghunathan, Srimat T. Chakradhar |
| 2005 | SECON | Battery discharge characteristics of wireless sensor nodes: an experimental analysis. | Chulsung Park, Kanishka Lahiri, Anand Raghunathan |
| 2004 | VLSID | Configurable Platforms With Dynamic Platform Management: An Efficient Alternative to Application-Specific System-on-Chips. | Krishna Sekar, Kanishka Lahiri, Sujit Dey |
| 2003 | ICCAD | Dynamic Platform Management for Configurable Platform-Based System-on-Chips. | Krishna Sekar, Kanishka Lahiri, Sujit Dey |
| 2002 | DAC | Communication architecture based power management for battery efficient system design. | Kanishka Lahiri, Sujit Dey, Anand Raghunathan |
| 2002 | VLSID | Embedded Tutorial: Battery-Driven System Design: A New Frontier in Low Power Design. | Kanishka Lahiri, Anand Raghunathan, Sujit Dey, Debashis Panigrahi |
| 2001 | DAC | LOTTERYBUS: A New High-Performance Communication Architecture for System-on-Chip Designs. | Kanishka Lahiri, Anand Raghunathan, Ganesh Lakshminarayana |
| 2001 | VLSID | Evaluation of the Traffic-Performance Characteristics of System-on-Chip Communication Architectures. | Kanishka Lahiri, Sujit Dey, Anand Raghunathan |
| 2001 | VLSID | Battery Life Estimation of Mobile Embedded Systems. | Debashis Panigrahi, Sujit Dey, Ramesh R. Rao, Kanishka Lahiri, Carla Fabiana Chiasserini, Anand Raghunathan |
| 2000 | DAC | Communication architecture tuners: a methodology for the design of high-performance communication architectures for systems-on-chips. | Kanishka Lahiri, Anand Raghunathan, Ganesh Lakshminarayana, Sujit Dey |
| 2000 | ICCAD | Efficient Exploration of the SoC Communication Architecture Design Space. | Kanishka Lahiri, Anand Raghunathan, Sujit Dey |
| 2000 | VLSID | Performance Analysis of Systems with Multi-Channel Communication Architectures. | Kanishka Lahiri, Sujit Dey, Anand Raghunathan |
| 1999 | ICCAD | Fast performance analysis of bus-based system-on-chip communication architectures. | Kanishka Lahiri, Anand Raghunathan, Sujit Dey |