| 2023 | ICASSP | Embedding a Differentiable Mel-Cepstral Synthesis Filter to a Neural Speech Synthesis System. | Takenori Yoshimura, Shinji Takaki, Kazuhiro Nakamura, Keiichiro Oura, Yukiya Hono, Kei Hashimoto, Yoshihiko Nankaku, Keiichi Tokuda |
| 2020 | ICASSP | Fast and High-Quality Singing Voice Synthesis System Based on Convolutional Neural Networks. | Kazuhiro Nakamura, Shinji Takaki, Kei Hashimoto, Keiichiro Oura, Yoshihiko Nankaku, Keiichi Tokuda |
| 2014 | ICASSP | HMM-Based singing voice synthesis and its application to Japanese and English. | Kazuhiro Nakamura, Keiichiro Oura, Yoshihiko Nankaku, Keiichi Tokuda |
| 2014 | ICASSP | Integration of speaker and pitch adaptive training for HMM-based singing voice synthesis. | Kanako Shirota, Kazuhiro Nakamura, Kei Hashimoto, Keiichiro Oura, Yoshihiko Nankaku, Keiichi Tokuda |
| 2014 | Interspeech | A mel-cepstral analysis technique restoring high frequency components from low-sampling-rate speech. | Kazuhiro Nakamura, Kei Hashimoto, Keiichiro Oura, Yoshihiko Nankaku, Keiichi Tokuda |
| 2013 | ICASSP | Integration of acoustic modeling and mel-cepstral analysis for HMM-based speech synthesis. | Kazuhiro Nakamura, Kei Hashimoto, Yoshihiko Nankaku, Keiichi Tokuda |
| 2008 | ICASSP | Acoustic modeling with contextual additive structure for HMM-based speech recognition. | Yoshihiko Nankaku, Kazuhiro Nakamura, Heiga Zen, Keiichi Tokuda |
| 2008 | ISCAS | Fast and memory efficient VLSI architecture for output probability computations of HMM-based recognition systems. | Kazuhiro Nakamura, Masatoshi Yamamoto, Kazuyoshi Takagi, Naofumi Takagi |
| 2007 | GLOBECOM | Scale-Free Property of Directed Networks with Two Intrinsic Node Weights. | Shigeo Shioda, Kazuhiro Nakamura |
| 2001 | ASPDAC | A real-time 64-monosyllable recognition LSI with learning mechanism. | Kazuhiro Nakamura, Qiang Zhu, Shinji Maruoka, Takashi Horiyama, Shinji Kimura, Katsumasa Watanabe |
| 2001 | ASPDAC | Speech recognition chip for monosyllables. | Kazuhiro Nakamura, Qiang Zhu, Shinji Maruoka, Takashi Horiyama, Shinji Kimura, Katsumasa Watanabe |
| 2000 | ASPDAC | Multi-clock path analysis using propositional satisfiability. | Kazuhiro Nakamura, Shinji Maruoka, Shinji Kimura, Katsumasa Watanabe |
| 1998 | ICCAD | Waiting false path analysis of sequential logic circuits for performance optimization. | Kazuhiro Nakamura, Kazuyoshi Takagi, Shinji Kimura, Katsumasa Watanabe |