Kazunori Shimizu
Publication record assembled from the DBLP archive of ranked conferences.
Papers indexed
6
Venues
4
Active years
2005–2008
Best venue rank
B
Where they publish
Papers
6 indexed papers, newest first.
| Year | Venue | Title | Authors |
|---|---|---|---|
| 2008 | ASPDAC | Scalable unified dual-radix architecture for Montgomery multiplication in GF(P) and GF(2 | Kazuyuki Tanimura, Ryuta Nara, Shunitsu Kohara, Kazunori Shimizu, Youhua Shi, Nozomu Togawa, Masao Yanagisawa, Tatsuo Ohtsuki |
| 2007 | ISLPED | Power-efficient LDPC code decoder architecture. | Kazunori Shimizu, Nozomu Togawa, Takeshi Ikenaga, Satoshi Goto |
| 2006 | ASPDAC | High-throughput decoder for low-density parity-check code. | Tatsuyuki Ishikawa, Kazunori Shimizu, Takeshi Ikenaga, Satoshi Goto |
| 2006 | ISCAS | A parallel LSI architecture for LDPC decoder improving message-passing schedule. | Kazunori Shimizu, Tatsuyuki Ishikawa, Nozomu Togawa, Takeshi Ikenaga, Satoshi Goto |
| 2005 | ASPDAC | Reconfigurable adaptive FEC system with interleaving. | Kazunori Shimizu, Nozomu Togawa, Takeshi Ikenaga, Satoshi Goto |
| 2005 | ICCD | Partially-Parallel LDPC Decoder Based on High-Efficiency Message-Passing Algorithm. | Kazunori Shimizu, Tatsuyuki Ishikawa, Takeshi Ikenaga, Satoshi Goto, Nozomu Togawa |