Kazutami Arimoto
Publication record assembled from the DBLP archive of ranked conferences.
Papers indexed
10
Venues
6
Active years
1985–2017
Best venue rank
A*
Where they publish
Papers
10 indexed papers, newest first.
| Year | Venue | Title | Authors |
|---|---|---|---|
| 2017 | PROFES | Tool Support for Consistency Verification of UML Diagrams. | Salilthip Phuklang, Tomoyuki Yokogawa, Pattara Leelaprute, Kazutami Arimoto |
| 2014 | DDECS | The LSI implementation of a memory based field programmable device for MCU peripherals. | Tetsuya Matsumura, Naoya Okada, Yoshifumi Kawamura, Koji Nii, Kazutami Arimoto, Hiroshi Makino, Yoshio Matsuda |
| 2013 | PRDC | Consistency Verification of UML Diagrams Based on Process Bisimulation. | Tomoyuki Yokogawa, Sousuke Amasaki, Keisuke Okazaki, Yoichiro Sato, Kazutami Arimoto, Hisashi Miyazaki |
| 2011 | CVPR | Implementation and evaluation of FAST corner detection on the massively parallel embedded processor MX-G. | Yushi Moko, Yoshihiro Watanabe, Takashi Komuro, Masatoshi Ishikawa, Masami Nakajima, Kazutami Arimoto |
| 2007 | ISCAS | Efficient Vertical/Horizontal-Space 1D-DCT Processing Based on Massive-Parallel Matrix-Processing Engine. | Takeshi Kumaki, Tetsushi Koide, Hans Jrgen Mattausch, Yasuto Kuroda, Hideyuki Noda, Katsumi Dosaka, Kazutami Arimoto, Kazunori Saito |
| 2005 | ISCAS | CAM-based VLSI architecture for Huffman coding with real-time optimization of the code word table [image coding example]. | Takeshi Kumaki, Yasuto Kuroda, Tetsushi Koide, Hans Jrgen Mattausch, Hideyuki Noda, Katsumi Dosaka, Kazutami Arimoto, Kazunori Saito |
| 2001 | ITC | Test cost reduction by at-speed BISR for embedded DRAMs. | Yoshihiro Nagura, Michael Mullins, Anthony Sauvageau, Yoshinoro Fujiwara, Katsuya Furue, Ryuji Ohmura, Tatsunori Komoike, Takenori Okitaka, Tetsushi Tanizaki, Katsumi Dosaka, Kazutami Arimoto, Yukiyoshi Koda, Tetsuo Tada |
| 1992 | ITC | A Testing Technique for ULSI Memory with On-Chip Voltage Down Converter. | Masaki Tsukude, Kazutami Arimoto, Hideto Hidaka, Yasuhiro Konishi, Masanori Hayashikoshi, Katsunori Suma, Kazuyasu Fujishima |
| 1989 | ITC | A New Array Architecture for Parallel Testing in VLSI Memories. | Yoshio Matsuda, Kazutami Arimoto, Masaki Tsukude, Tsukasa Oishi, Kazuyasu Fujishima |
| 1985 | ITC | Test Pattern Considerations for Fault Tolerant High Density DRAM. | Hiroshi Miyamoto, Koichiro Mashiko, Yoshikazu Morooka, Kazutami Arimoto, Michihiro Yamada, Takao Nakano |