Keiichi Higeta
Publication record assembled from the DBLP archive of ranked conferences.
Papers indexed
2
Venues
1
Active years
1999–2005
Best venue rank
A
Where they publish
Papers
2 indexed papers, newest first.
| Year | Venue | Title | Authors |
|---|---|---|---|
| 2005 | ITC | External memory BIST for system-in-package. | Kaname Yamasaki, Iwao Suzuki, Azumi Kobayashi, Keiichi Horie, Yasuharu Kobayashi, Hideyuki Aoki, Hideki Hayashi, Kenichi Tada, Koki Tsutsumida, Keiichi Higeta |
| 1999 | ITC | Built-in self-test for GHz embedded SRAMs using flexible pattern generator and new repair algorithm. | Shigeru Nakahara, Keiichi Higeta, Masaki Kohno, Toshiaki Kawamura, Keizo Kakitani |