Keiji Kishine
Publication record assembled from the DBLP archive of ranked conferences.
Papers indexed
7
Venues
2
Active years
2000–2022
Best venue rank
B
Where they publish
Papers
7 indexed papers, newest first.
| Year | Venue | Title | Authors |
|---|---|---|---|
| 2022 | ASPDAC | Supply-Variation-Tolerant Transimpedance Amplifier Using Non-Inverting Amplifier in 180-nm CMOS. | Tomofumi Tsuchida, Akira Tsuchiya, Toshiyuki Inoue, Keiji Kishine |
| 2021 | ASPDAC | Supply Noise Reduction Filter for Parallel Integrated Transimpedance Amplifiers. | Shinya Tanimura, Akira Tsuchiya, Toshiyuki Inoue, Keiji Kishine |
| 2017 | ISCAS | 25-Gb/s clock and data recovery IC using latch-load combined with CML buffer circuit for delay generation with 65-nm CMOS. | Tomonori Tanaka, Kosuke Furuichi, Hiromu Uemura, Ryosuke Noguchi, Natsuyuki Koda, Koki Arauchi, Daichi Omoto, Hiromi Inaba, Keiji Kishine, Shinsuke Nakano, Masafumi Nogawa, Hideyuki Nosaka |
| 2014 | ISCAS | A 65-nm CMOS burst-mode CDR based on a GVCO with symmetric loops. | Keiji Kishine, Hiroshi Inoue, Hiromi Inaba, Makoto Nakamura, Akira Tsuchiya, Hidetoshi Onodera, Hiroaki Katsurai |
| 2013 | ASPDAC | A 25-Gb/s LD driver with area-effective inductor in a 0.18-m CMOS. | Takeshi Kuboki, Yusuke Ohtomo, Akira Tsuchiya, Keiji Kishine, Hidetoshi Onodera |
| 2012 | ASPDAC | A 16Gb/s area-efficient LD driver with interwoven inductor in a 0.18m CMOS. | Takeshi Kuboki, Yusuke Ohtomo, Akira Tsuchiya, Keiji Kishine, Hidetoshi Onodera |
| 2000 | ISCAS | A jitter suppression technique for a 2.48832 Gb/s clock and data recovery circuit. | Kiyoshi Ishii, Keiji Kishine, Haruhiko Ichino |