Kichiji Hatanaka
Publication record assembled from the DBLP archive of ranked conferences.
Papers indexed
2
Venues
2
Active years
2008–2011
Best venue rank
C
Where they publish
Papers
2 indexed papers, newest first.
| Year | Venue | Title | Authors |
|---|---|---|---|
| 2011 | IOLTS | Investigation of multi cell upset in sequential logic and validity of redundancy technique. | Taiki Uemura, Takashi Kato, Hideya Matsuyama, Keiji Takahisa, Mitsuhiro Fukuda, Kichiji Hatanaka |
| 2008 | DSN | Validation of hardware error recovery mechanisms for the SPARC64 V microprocessor. | Hisashige Ando, Ryuji Kan, Yoshiharu Tosaka, Keiji Takahisa, Kichiji Hatanaka |