Kishore Kasamsetty
Publication record assembled from the DBLP archive of ranked conferences.
Papers indexed
1
Venues
1
Active years
2000–2000
Best venue rank
A*
Where they publish
Papers
1 indexed papers, newest first.
| Year | Venue | Title | Authors |
|---|---|---|---|
| 2000 | DAC | Convex delay models for transistor sizing. | Mahesh Ketkar, Kishore Kasamsetty, Sachin S. Sapatnekar |