Kiyoshi Takeshita
Publication record assembled from the DBLP archive of ranked conferences.
Papers indexed
1
Venues
1
Active years
2008–2008
Best venue rank
A
Where they publish
Papers
1 indexed papers, newest first.
| Year | Venue | Title | Authors |
|---|---|---|---|
| 2008 | ITC | Power-Aware At-Speed Scan Test Methodology for Circuits with Synchronous Clocks. | Benoit Nadeau-Dostie, Kiyoshi Takeshita, Jean-Francois Cote |