Koichi Nose
Publication record assembled from the DBLP archive of ranked conferences.
Papers indexed
4
Venues
2
Active years
2000–2002
Best venue rank
A
Where they publish
Papers
4 indexed papers, newest first.
| Year | Venue | Title | Authors |
|---|---|---|---|
| 2002 | ISLPED | Power-conscious interconnect buffer optimization with improved modeling of driver MOSFET and Its implications to bulk and SOI CMOS technology. | Koichi Nose, Takayasu Sakurai |
| 2001 | ISLPED | Design methodology and optimization strategy for dual-VTH scheme using commercially available tools. | Masayuki Hirabayashi, Koichi Nose, Takayasu Sakurai |
| 2000 | ASPDAC | Optimization of VDD and VTH for low-power and high speed applications. | Koichi Nose, Takayasu Sakurai |
| 2000 | ISLPED | Voltage dependent gate capacitance and its impact in estimating power and delay of CMOS digital circuits with low supply voltage (poster session). | Koichi Nose, Soo-Ik Chae, Takayasu Sakurai |