Kyosei Yanagida
Publication record assembled from the DBLP archive of ranked conferences.
Papers indexed
1
Venues
1
Active years
2014–2014
Best venue rank
B
Where they publish
Papers
1 indexed papers, newest first.
| Year | Venue | Title | Authors |
|---|---|---|---|
| 2014 | FPL | A logic cell architecture exploiting the shannon expansion for the reduction of configuration memory. | Qian Zhao, Kyosei Yanagida, Motoki Amagasaki, Masahiro Iida, Morihiro Kuga, Toshinori Sueyoshi |