| 2026 | DATE | Dynamic Neural Thresholding on Mixed-Signal Neuromorphic Processors Enabled by Integrated Learning and Hardware Design. | Kyuseung Han, Kwang-Il Oh, Sukho Lee, Hyeonguk Jang, Jae-Jin Lee, Sooyoung Jang |
| 2025 | FPL | NPX: Automating Neuromorphic Processor Design from Spike-Based Learning to FPGA Prototyping. | Kyuseung Han, Hyeonguk Jang, Sukho Lee, Sung-Eun Kim, Kyudong Hwang, Jae-Jin Lee |
| 2025 | FPL | NeuGEMM: A Reordering-Free Unified GEMM-Conv2D Accelerator for Lightweight Neuromorphic Processors. | Hyeonguk Jang, Sukho Lee, Jae-Jin Lee, Kyuseung Han |
| 2024 | ISLPED | STARC: Crafting Low-Power Mixed-Signal Neuromorphic Processors by Bridging SNN Frameworks and Analog Designs. | Kyuseung Han, Hyunseok Kwak, Kwang-Il Oh, Sukho Lee, Hyeonguk Jang, Jae-Jin Lee, Woojoo Lee |
| 2023 | DATE | Developing an Ultra-low Power RISC-V Processor for Anomaly Detection. | Jina Park, Eunjin Choi, Kyungwon Lee, Jae-Jin Lee, Kyuseung Han, Woojoo Lee |
| 2023 | ISLPED | Florian: Developing a Low-Power RISC-V Multicore Processor with a Shared Lightweight FPU. | Jina Park, Kyuseung Han, Eunjin Choi, Sukho Lee, Jae-Jin Lee, Woojoo Lee, Massoud Pedram |
| 2019 | ISLPED | TIP: A Temperature Effect Inversion-Aware Ultra-Low Power System-on-Chip Platform. | Kyuseung Han, Sukho Lee, Jae-Jin Lee, Woojoo Lee, Massoud Pedram |
| 2014 | ASPDAC | Leveraging parallelism in the presence of control flow on CGRAs. | Jihyun Ryoo, Kyuseung Han, Kiyoung Choi |
| 2013 | DATE | Compiling control-intensive loops for CGRAs with state-based full predication. | Kyuseung Han, Kiyoung Choi, Jongeun Lee |
| 2012 | DATE | State-based full predication for low power coarse-grained reconfigurable architecture. | Kyuseung Han, Seongsik Park, Kiyoung Choi |