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Larry G. Jones

Publication record assembled from the DBLP archive of ranked conferences.

Papers indexed

9

Venues

5

Active years

1986–1997

Best venue rank

A*

Where they publish

Papers

9 indexed papers, newest first.

YearVenueTitleAuthors
1997DACCELLERITY: A Fully Automatic Layout Synthesis System for Standard Cell Libraries.Mohankumar Guruswamy, Robert L. Maziasz, Daniel Dulitz, Srilata Raman, Venkat Chiluvuri, Andrea Fernndez, Larry G. Jones
1997DATEFast power loss calculation for digital static CMOS circuits.Sergey Gavrilov, Alexey Glebov, Sergey G. Rusakov, David T. Blaauw, Larry G. Jones, Gopalakrishnan Vijayan
1996DATEA Timing-Constrained Incremental Routing Algorithm for Symmetrical FPGAs.Srilata Raman, C. L. Liu, Larry G. Jones
1995ISLPEDTransistor reordering for low power CMOS gates using an SP-BDD representation.Alexey Glebov, David T. Blaauw, Larry G. Jones
1992DACZero Delay versus Positive Delay in an Incremental Switch-Level Simulator.Larry G. Jones
1991DACAccelerating Switch-Level Simulation by Function Caching.Larry G. Jones
1989DACFast Online/Offline Netlist Compilation of Hierarchical Schematics.Larry G. Jones
1989ICCADFast incremental netlist compilation of hierarchical schematics.Larry G. Jones
1986POPLHierarchical VLSI Design Systems Based on Attribute Grammars.Larry G. Jones, Janos Simon