Luo Jianwen
Publication record assembled from the DBLP archive of ranked conferences.
Papers indexed
1
Venues
1
Active years
2004–2004
Best venue rank
C
Where they publish
Papers
1 indexed papers, newest first.
| Year | Venue | Title | Authors |
|---|---|---|---|
| 2004 | DSD | Partially Reconfigurable Matrix Multiplication for Area and Time Efficiency on FPGAs. | Luo Jianwen, Jong Ching Chuen |