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M. H. Vasantha

Publication record assembled from the DBLP archive of ranked conferences.

Papers indexed

9

Venues

3

Active years

2016–2023

Best venue rank

C

Where they publish

Papers

9 indexed papers, newest first.

YearVenueTitleAuthors
2023ISCASA 11-ns, 3.85-fJ, Deep Sub-threshold, Energy Efficient Level Shifter in 65-nm CMOS.R. D. Balaji, Siddharth R. K., Sanmitra Bharat Naik, Y. B. Nithin Kumar, M. H. Vasantha, Edoardo Bonizzoni
2022ISCASOn The Design Of Rationalised Bi-orthogonal Wavelet Using Reversible Logic.Sithara Raveendran, Pranose J. Edavoor, Y. B. Nithin Kumar, M. H. Vasantha
2021VLSIDA 1 V Double-Balanced Mixer for 2.4-2.5 GHz ISM Band Applications.Sanmitra Bharat Naik, Siddharth R. K., Anirban Chatterjee, Kumar Y. B. Nithin, M. H. Vasantha, Ramnath Kini
2019TenconCurrent Conveyor based Novel Gyrator filter for Biomedical Sensor Applications.P. S. Veerendranath, Vivek Sharma, Nithin Y. B. Kumar, M. H. Vasantha, Edoardo Bonizzoni
2018ISCASA Low-Power Auxiliary Circuit for Level-Crossing ADCs in IoT-Sensor Applications.Siddharth R. K., Kumar Y. B. Nithin, M. H. Vasantha, Edoardo Bonizzoni
2018VLSIDA Novel Low Power G m-C Continuous-Time Analog Filter with Wide Tuning Range.P. S. Veerendranath, M. H. Vasantha, Kumar Y. B. Nithin, Edoardo Bonizzoni
2018TenconDesign and Implementation of Reversible Logic based RGB to Gray scale Color Space Converter.Sithara Raveendran, Pranose J. Edavoor, Nithin Y. B. Kumar, M. H. Vasantha
2018TenconCharacterization of a Novel Low Leakage Power-Efficient Asymmetric 7T SRAM Cell.Dhavala Shashidhar, Vivek Sharma, Gurusiddappa R. Prashanth, Nithin Y. B. Kumar, M. H. Vasantha
2016VLSIDCharacterization of a Novel Low Leakage Power and Area Efficient 7T SRAM Cell.A. Venkatareddy, Sithara Raveendran, Kumar Y. B. Nithin, M. H. Vasantha