M. S. Hrishikesh
Publication record assembled from the DBLP archive of ranked conferences.
Papers indexed
3
Venues
2
Active years
2000–2002
Best venue rank
A*
Where they publish
Papers
3 indexed papers, newest first.
| Year | Venue | Title | Authors |
|---|---|---|---|
| 2002 | ISCA | The Optimal Logic Depth Per Pipeline Stage is 6 to 8 FO4 Inverter Delays. | M. S. Hrishikesh, Doug Burger, Stephen W. Keckler, Premkishore Shivakumar, Norman P. Jouppi, Keith I. Farkas |
| 2001 | ICCD | Static Energy Reduction Techniques for Microprocessor Caches. | Heather Hanson, M. S. Hrishikesh, Vikas Agarwal, Stephen W. Keckler, Doug Burger |
| 2000 | ISCA | Clock rate versus IPC: the end of the road for conventional microarchitectures. | Vikas Agarwal, M. S. Hrishikesh, Stephen W. Keckler, Doug Burger |