Mahendra Sakare
Publication record assembled from the DBLP archive of ranked conferences.
Papers indexed
5
Venues
3
Active years
2011–2025
Best venue rank
C
Where they publish
Papers
5 indexed papers, newest first.
| Year | Venue | Title | Authors |
|---|---|---|---|
| 2025 | ISCAS | A 2.9mW Inverter-based Quadrature Phase Clock Generator with ± 0.29° Phase Error. | Mayank Kumar Singh, M. Bhuvanesh, Rajasekhar Nagulapalli, Devarshi Mrinal Das, Mahendra Sakare |
| 2016 | VLSID | A 12.5 Gbps One-Fifth Rate CDR Incorporating a Novel Sampler Based Phase Detector and a DFE. | Pragya Maheshwari, Suhas Kaushik, Mahendra Sakare, Shalabh Gupta |
| 2016 | VLSID | A Quarter-Rate 27-1 Pseudo-Random Binary Sequence Generator Using Interleaved Architecture. | Mahendra Sakare |
| 2014 | ISCAS | A high-speed PRBS generator using flip-flops employing feedback for distributed equalization. | Mahendra Sakare, Shalabh Gupta |
| 2011 | DATE | Testing of high-speed DACs using PRBS generation with "Alternate-Bit-Tapping". | Mohit Singh, Mahendra Sakare, Shalabh Gupta |