| 2017 | ETS | Design of a sinusoidal signal generator with calibrated harmonic cancellation for mixed-signal BIST in a 28 nm FDSOI technology. | Hani Malloug, Manuel J. Barragan Asian, Salvador Mir, Laurent Basteres, Herv Le Gall |
| 2013 | ETS | Efficient selection of signatures for analog/RF alternate test. | Manuel J. Barragan Asian, Gildas Lger |
| 2012 | ETS | OBT for settling error test of sampled-data systems using signal-dependent clocking. | Manuel J. Barragan Asian, Gildas Lger, Jos L. Huertas |
| 2010 | ETS | Low-cost signature test of RF blocks based on envelope response analysis. | Manuel J. Barragan Asian, Rafaella Fiorelli, Diego Vzquez, Adoracin Rueda, Jos Luis Huertas |
| 2010 | ISCAS | On-chip biased voltage-controlled oscillator with temperature compensation of the oscillation amplitude for robust I/Q generation. | Antonio J. Gins, Ricardo Doldn, Manuel J. Barragan Asian, Adoracin Rueda, Eduardo J. Peralas |
| 2008 | DATE | Practical Implementation of a Network Analyzer for Analog BIST Applications. | Manuel J. Barragan Asian, Diego Vzquez, Adoracin Rueda |
| 2007 | DATE | Interactive presentation: BIST method for die-level process parameter variation monitoring in analog/mixed-signal integrated circuits. | Amir Zjajo, Manuel J. Barragan Asian, Jos Pineda de Gyvez |
| 2006 | DDECS | A Sinewave Analyzer for Mixed-Signal BIST Applications in a 0.35m Technology. | Manuel J. Barragan Asian, Diego Vzquez, Adoracin Rueda |