Manuel Valencia
Publication record assembled from the DBLP archive of ranked conferences.
Papers indexed
1
Venues
1
Active years
2000–2000
Best venue rank
C
Where they publish
Papers
1 indexed papers, newest first.
| Year | Venue | Title | Authors |
|---|---|---|---|
| 2000 | ISCAS | Inertial and degradation delay model for CMOS logic gates. | Jorge Juan-Chico, Paulino Ruiz-de-Clavijo, Manuel J. Bellido, Antonio J. Acosta, Manuel Valencia |