| 2025 | FPL | Live Demonstration: Continuous Processing of Event-Data with Graph Convolutional Neural Networks Implemented for SoC FPGA. | Piotr Wzorek, Kamil Jeziorek, Marcin Kowalczyk, Krzysztof Blachut, Tomasz Kryjak, Marek Gorgon |
| 2024 | DSD | PowerYOLO: Mixed Precision Model for Hardware Efficient Object Detection with Event Data. | Dominika Przewlocka-Rus, Tomasz Kryjak, Marek Gorgon |
| 2021 | FPL | Hardware-software implementation of a DNN for 3D object detection using FINN - a demo. | Joanna Stanisz, Konrad Lis, Tomasz Kryjak, Marek Gorgon |
| 2020 | ICCVG | A Vision Based Hardware-Software Real-Time Control System for the Autonomous Landing of an UAV. | Krzysztof Blachut, Hubert Szolc, Mateusz Wasala, Tomasz Kryjak, Marek Gorgon |
| 2019 | CVPR | Melanoma Thickness Prediction Based on Convolutional Neural Network With VGG-19 Model Transfer Learning. | Joanna Jaworek-Korjakowska, Pawel Kleczek, Marek Gorgon |
| 2017 | FedCSIS | H.265 Inverse Transform FPGA implementation in Impulse C. | Slawomir Cichon, Marek Gorgon |
| 2015 | ICIAP | Real-Time Implementation of Background Modelling Algorithms in FPGA Devices. | Tomasz Kryjak, Marek Gorgon |
| 2014 | ICCVG | Implementation of Advanced Foreground Segmentation Algorithms GMM, ViBE and PBAS in FPGA and GPU - A Comparison. | Bartlomiej Bulat, Tomasz Kryjak, Marek Gorgon |
| 2013 | FedCSIS | Real-time Implementation of the ViBe Foreground Object Segmentation Algorithm. | Tomasz Kryjak, Marek Gorgon |
| 2012 | FPL | Floating point HOG implementation for real-time multiple object detection. | Mateusz Komorkiewicz, Maciej Kluczewski, Marek Gorgon |
| 2009 | FPL | Pipeline implementation of the 128-bit block cipher CLEFIA in FPGA. | Tomasz Kryjak, Marek Gorgon |
| 2007 | DSD | FPGA-based Road Traffic Videodetector. | Marek Gorgon, Piotr Pawlik, Miroslaw Jablonski, Jaromir Przybylo |
| 2007 | FCCM | PixelStreams-based implementation of videodetector. | Marek Gorgon, Piotr Pawlik, Miroslaw Jablonski, Jaromir Przybylo |
| 2006 | ICAISC | Neural Network Implementation in Reprogrammable FPGA Devices - An Example for MLP. | Marek Gorgon, Mateusz Wrzesinski |
| 2005 | FPL | Real-time Handel-C Based Implementation of DV Decoder. | Marek Gorgon, Slawomir Cichon, Miroslaw Pac |
| 2004 | DSD | Handel-C implementation of Classical Component Labelling Algorithm. | Miroslaw Jablonski, Marek Gorgon |
| 2001 | DSD | FPGA Based Controller for Heterogeneous Image Processing System. | Marek Gorgon, Jaromir Przybylo |