| 2015 | INDIN | Design environment for hardware generation of SLFF neural network topologies with ELM training capability. | Jos Miguel Martnez-Villena, Jos Vicente Francs-Vllora, Alfredo Rosado Muoz, Manuel Bataller-Mompen, Juan-Francisco Guerrero-Martnez, Marek Wegrzyn, Marian Adamski |
| 2014 | DEPCoS | Model Checking of UML Activity Diagrams in Logic Controllers Design. | Iwona Grobelna, Michal Grobelny, Marian Adamski |
| 2014 | HSI | Translation UML diagrams into Verilog. | Grzegorz Bazydlo, Marian Adamski, Lukasz Stefanowicz |
| 2014 | HSI | Dual synthesis of Petri net based dependable logic controllers for safety critical systems. | Arkadiusz Bukowiec, Jacek Tkacz, Marian Adamski, Remigiusz Wisniewski |
| 2014 | HSI | Aspects of selection of SM Components with the application of the theory of hypergraphs. | Lukasz Stefanowicz, Marian Adamski |
| 2014 | HSI | FPGA-based embedded Logic Controllers. | Marek Wegrzyn, Marian Adamski, Andrei Karatkevich, Alfredo Rosado Muoz |
| 2014 | HSI | Application of comparability graphs in decomposition of Petri nets. | Remigiusz Wisniewski, Andrei Karatkevich, Marian Adamski, Daniel Kur |
| 2013 | INDIN | UML state machine implementation in FPGA devices by means of dual model and Verilog. | Michal Doligalski, Marian Adamski |
| 2012 | DDECS | Synthesis of Petri nets into FPGA with operation flexible memories. | Arkadiusz Bukowiec, Marian Adamski |
| 2011 | ICSEng | Exceptions Handling in Hierarchical Petri Net Based Specification for Logic Controllers. | Michal Doligalski, Marian Adamski |
| 2011 | ICSEng | Role of UML Modelling in Discrete Controller Design. | Grzegorz Labiak, Marian Adamski, Jacek Tkacz, Michal Doligalski, Arkadiusz Bukowiec |
| 1998 | SMC | SFC, Petri nets and application specific logic controllers. | Marian Adamski |