Mario Steinert
Publication record assembled from the DBLP archive of ranked conferences.
Papers indexed
3
Venues
2
Active years
2002–2004
Best venue rank
C
Where they publish
Papers
3 indexed papers, newest first.
| Year | Venue | Title | Authors |
|---|---|---|---|
| 2004 | DATE | RTL Processor Synthesis for Architecture Exploration and Implementation. | Oliver Schliebusch, Anupam Chattopadhyay, Rainer Leupers, Gerd Ascheid, Heinrich Meyr, Mario Steinert, Gunnar Braun, Achim Nohl |
| 2004 | ISCAS | Power consumption optimization for low latency Viterbi Decoder. | Mario Steinert, Stefano Marsili |
| 2002 | ISCAS | Testability of path history memories with register-exchange architecture used in Viterbi-decoders. | Stefan R. Meier, Mario Steinert, Steffen Buch |