| 2015 | ASPDAC | Synthesis of resonant clock networks supporting dynamic voltage / frequency scaling. | Seyong Ahn, Minseok Kang, Marios C. Papaefthymiou, Taewhan Kim |
| 2013 | ASPLOS | Computational sprinting on a hardware/software testbed. | Arun Raghavan, Laurel Emurian, Lei Shao, Marios C. Papaefthymiou, Kevin P. Pipe, Thomas F. Wenisch, Milo M. K. Martin |
| 2012 | HPCA | Computational sprinting. | Arun Raghavan, Yixin Luo, Anuj Chandawalla, Marios C. Papaefthymiou, Kevin P. Pipe, Thomas F. Wenisch, Milo M. K. Martin |
| 2005 | DATE | RIP: An Efficient Hybrid Repeater Insertion Scheme for Low Power. | Xun Liu, Yuantao Peng, Marios C. Papaefthymiou |
| 2005 | ISLPED | A GHz-class charge recovery logic. | Visvesh S. Sathe, Marios C. Papaefthymiou, Conrad H. Ziesler |
| 2005 | PDCAT | Multi-Session Partitioning for Parallel Timing Optimization. | Jiyoun Kim, Jos Neves, Marios C. Papaefthymiou |
| 2004 | DAC | Practical repeater insertion for low power: what repeater library do we need? | Xun Liu, Yuantao Peng, Marios C. Papaefthymiou |
| 2004 | ISCAS | Empirical evaluation of timing and power in resonant clock distribution. | Juang-Ying Chueh, Conrad H. Ziesler, Marios C. Papaefthymiou |
| 2004 | ISLPED | Constant-load energy recovery memory for efficient high-speed operation. | Joohee Kim, Marios C. Papaefthymiou |
| 2003 | ASPDAC | HyPE: hybrid power estimation for IP-based programmable systems. | Xun Liu, Marios C. Papaefthymiou |
| 2003 | DATE | Reduced Delay Uncertainty in High Performance Clock Distribution Networks. | Dimitrios Velenis, Marios C. Papaefthymiou, Eby G. Friedman |
| 2003 | ISLPED | A 225 MHz resonant clocked ASIC chip. | Conrad H. Ziesler, Joohee Kim, Visvesh S. Sathe, Marios C. Papaefthymiou |
| 2002 | DAC | Design of a high-throughput low-power IS95 Viterbi decoder. | Xun Liu, Marios C. Papaefthymiou |
| 2002 | ICCAD | A Markov chain sequence generator for power macromodeling. | Xun Liu, Marios C. Papaefthymiou |
| 2002 | ISCAS | Incorporation of input glitches into power macromodeling. | Xun Liu, Marios C. Papaefthymiou |
| 2002 | ISLPED | Energy recovering static memory. | Joohee Kim, Conrad H. Ziesler, Marios C. Papaefthymiou |
| 2001 | DAC | A True Single-Phase 8-bit Adiabatic Multiplier. | Suhwan Kim, Conrad H. Ziesler, Marios C. Papaefthymiou |
| 2001 | DATE | A static power estimation methodolodgy for IP-based design. | Xun Liu, Marios C. Papaefthymiou |
| 2001 | ISCAS | A clock tree topology extraction algorithm for improving the tolerance of clock distribution networks to delay uncertainty. | Dimitrios Velenis, Eby G. Friedman, Marios C. Papaefthymiou |
| 2001 | ISLPED | A resonant clock generator for single-phase adiabatic systems. | Conrad H. Ziesler, Suhwan Kim, Marios C. Papaefthymiou |
| 2000 | ASPDAC | Symbolic debugging of globally optimized behavioral specifications. | Inki Hong, Darko Kirovski, Miodrag Potkonjak, Marios C. Papaefthymiou |
| 1999 | DAC | Maximizing Performance by Retiming and Clock Skew Scheduling. | Xun Liu, Marios C. Papaefthymiou, Eby G. Friedman |
| 1999 | DATE | Minimizing Sensitivity to Delay Variations in High-Performance Synchronous Circuits. | Xun Liu, Marios C. Papaefthymiou, Eby G. Friedman |
| 1999 | ICCAD | Analytical macromodeling for high-level power estimation. | Giuseppe Bernacchia, Marios C. Papaefthymiou |
| 1999 | ISLPED | Single-phase source-coupled adiabatic logic. | Suhwan Kim, Marios C. Papaefthymiou |
| 1998 | ICCAD | Asymptotically efficient retiming under setup and hold constraints. | Marios C. Papaefthymiou |
| 1998 | ISLPED | True single-phase energy-recovering logic for low-power, high-speed VLSI. | Suhwan Kim, Marios C. Papaefthymiou |
| 1997 | JSSPP | Performance Evaluation of Gang Scheduling for Parallel and Distributed Multiprogramming. | Fang Wang, Marios C. Papaefthymiou, Mark S. Squillante |
| 1996 | DAC | Optimizing Systems for Effective Block-Processing: The | Kumar N. Lalgudi, Marios C. Papaefthymiou, Miodrag Potkonjak |
| 1996 | ISLPED | Fixed-phase retiming for low power design. | Marios C. Papaefthymiou, Kumar N. Lalgudi |
| 1996 | JSSPP | A Gang Scheduling Design for Multiprogrammed Parallel Computing Environments. | Fang Wang, Hubertus Franke, Marios C. Papaefthymiou, Pratap Pattnaik, Larry Rudolph, Mark S. Squillante |
| 1996 | SPAA | An Analysis of Gang Scheduling for Multiprogrammed Parallel Computing Environments. | Mark S. Squillante, Fang Wang, Marios C. Papaefthymiou |
| 1995 | DAC | DELAY: An Efficient Tool for Retiming with Realistic Delay Modeling. | Kumar N. Lalgudi, Marios C. Papaefthymiou |
| 1994 | ICCAD | Precomputation-based sequential logic optimization for low power. | Mazhar Alidina, Jos Monteiro, Srinivas Devadas, Abhijit Ghosh, Marios C. Papaefthymiou |
| 1993 | DAC | TIM: A Timing Package for Two-Phase, Level-Clocked Circuitry. | Marios C. Papaefthymiou, Keith H. Randall |
| 1991 | SPAA | Understanding Retiming Through Maximum Average-Weight Cycles. | Marios C. Papaefthymiou |