| 2026 | DATE | Optimizing Multibit Flip-Flop Banking via Agile In-Placement PPA Co-Optimization. | Huan-Yuan Chen, Yu-Ruei Lin, Mark Po-Hung Lin, Hung-Ming Chen |
| 2024 | DAC | Voronoi Diagram-based Multiple Power Plane Generation on Redistribution Layers in 3D ICs. | Chia-Wei Lin, Jing-Yao Weng, I-Te Lin, Ho-Chieh Hsu, Chia-Ming Liu, Mark Po-Hung Lin |
| 2023 | ASPDAC | On Automating Finger-Cap Array Synthesis with Optimal Parasitic Matching for Custom SAR ADC. | Cheng-Yu Chiang, Chia-Lin Hu, Mark Po-Hung Lin, Yu-Szu Chung, Shyh-Jye Jou, Jieh-Tsorng Wu, Shiuh-Hua Wood Chiang, Chien-Nan Jimmy Liu, Hung-Ming Chen |
| 2023 | DAC | Late Breaking Results: PVT-Sensitive Delay Fitting for High-Performance Computing. | Ding-Hao Wang, Shuo-Hung Hsu, Shu-Hsiang Yang, Pei-Ju Lin, Hui-Ting Yang, Mark Po-Hung Lin |
| 2022 | ASPDAC | Common-Centroid Layout for Active and Passive Devices: A Review and the Road Ahead. | Nibedita Karmokar, Meghna Madhusudan, Arvind K. Sharma, Ramesh Harjani, Mark Po-Hung Lin, Sachin S. Sapatnekar |
| 2021 | ASPDAC | A Novel Technology Mapper for Complex Universal Gates. | Meng-Che Wu, Ai Quoc Dao, Mark Po-Hung Lin |
| 2021 | DAC | A Novel Machine-Learning based SoC Performance Monitoring Methodology under Wide-Range PVT Variations with Unknown Critical Paths. | Ding-Hao Wang, Pei-Ju Lin, Hui-Ting Yang, Ching-An Hsu, Sin-Han Huang, Mark Po-Hung Lin |
| 2020 | DAC | Late Breaking Results: Pole-aware Analog Placement Considering Monotonic Current Flow and Crossing-Wire Minimization. | Abhishek Patyal, Hung-Ming Chen, Mark Po-Hung Lin |
| 2020 | DAC | Late Breaking Results: Automatic Adaptive MOM Capacitor Cell Generation for Analog and Mixed-Signal Layout Design. | Tzu-Wei Wang, Po-Chang Wu, Mark Po-Hung Lin |
| 2020 | ICCAD | Achieving Analog Layout Integrity through Learning and Migration Invited Talk. | Mark Po-Hung Lin, Hao-Yu Chi, Abhishek Patyal, Zheng-Yao Liu, Jun-Jie Zhao, Chien-Nan Jimmy Liu, Hung-Ming Chen |
| 2020 | ICCAD | Overview of 2020 CAD Contest at ICCAD. | Ing-Chao Lin, Ulf Schlichtmann, Tsung-Wei Huang, Mark Po-Hung Lin |
| 2019 | DATE | IR-aware Power Net Routing for Multi-Voltage Mixed-Signal Design. | Shuo-Hui Wang, Guan-Hong Liou, Yen-Yu Su, Mark Po-Hung Lin |
| 2019 | ICCAD | Overview of 2019 CAD Contest at ICCAD. | Ulf Schlichtmann, Sabya Das, Ing-Chao Lin, Mark Po-Hung Lin |
| 2018 | DAC | Efficient computation of ECO patch functions. | Ai Quoc Dao, Nian-Ze Lee, Li-Cheng Chen, Mark Po-Hung Lin, Jie-Hong R. Jiang, Alan Mishchenko, Robert K. Brayton |
| 2017 | DATE | High-density MOM capacitor array with novel mortise-tenon structure for low-power SAR ADC. | Nai-Chen Chen, Pang-Yen Chou, Helmut E. Graeb, Mark Po-Hung Lin |
| 2017 | ICCAD | State retention for power gated design with non-uniform multi-bit retention latches. | Guo-Gin Fan, Mark Po-Hung Lin |
| 2016 | ASPDAC | Recent research development and new challenges in analog layout synthesis. | Mark Po-Hung Lin, Yao-Wen Chang, Chih-Ming Hung |
| 2016 | DAC | Novel CMOS RFIC layout generation with concurrent device placement and fixed-length microstrip routing. | Tsun-Ming Tseng, Bing Li, Ching-Feng Yeh, Hsiang-Chieh Jhan, Zuo-Min Tsai, Mark Po-Hung Lin, Ulf Schlichtmann |
| 2014 | DAC | Parasitic-aware Sizing and Detailed Routing for Binary-weighted Capacitors in Charge-scaling DAC. | Mark Po-Hung Lin, Vincent Wei-Hao Hsiao, Chun-Yu Lin |
| 2014 | ICCAD | More effective power-gated circuit optimization with multi-bit retention registers. | Shu-Hung Lin, Mark Po-Hung Lin |
| 2013 | ICCAD | In-placement clock-tree aware multi-bit flip-flop generation for power optimization. | Chih-Cheng Hsu, Yu-Chuan Chen, Mark Po-Hung Lin |
| 2012 | ASPDAC | Crosstalk-aware power optimization with multi-bit flip-flops. | Chih-Cheng Hsu, Yao-Tsung Chang, Mark Po-Hung Lin |
| 2012 | ICCAD | Performance-driven analog placement considering monotonic current paths. | Po-Hsun Wu, Mark Po-Hung Lin, Yang-Ru Chen, Bing-Shiun Chou, Tung-Chieh Chen, Tsung-Yi Ho, Bin-Da Liu |
| 2011 | ICCAD | A corner stitching compliant B | Hui-Fang Tsao, Pang-Yen Chou, Shih-Lun Huang, Yao-Wen Chang, Mark Po-Hung Lin, Duan-Ping Chen, Dick Liu |
| 2010 | ICCAD | Post-placement power optimization with multi-bit flip-flops. | Yao-Tsung Chang, Chih-Cheng Hsu, Mark Po-Hung Lin, Yu-Wen Tsai, Sheng-Fong Chen |
| 2009 | DAC | Thermal-driven analog placement considering device matching. | Mark Po-Hung Lin, Hongbo Zhang, Martin D. F. Wong, Yao-Wen Chang |
| 2009 | DATE | Analog layout synthesis - Recent advances in topological approaches. | Helmut Grb, Florin Balasa, Rafael Castro-Lpez, Yu-Wei Chang, Francisco V. Fernndez, Mark Po-Hung Lin, Martin Strasser |
| 2008 | DAC | Analog placement based on hierarchical module clustering. | Mark Po-Hung Lin, Shyh-Chang Lin |
| 2007 | DAC | Analog Placement Based on Novel Symmetry-Island Formulation. | Mark Po-Hung Lin, Shyh-Chang Lin |