| 2007 | EUC | An Efficient Code Generation Algorithm for Code Size Reduction Using 1-Offset P-Code Queue Computation Model. | Arquimedes Canedo, Ben A. Abderazek, Masahiro Sowa |
| 2007 | PDCAT | New Code Generation Algorithm for QueueCore - An Embedded Processor with High ILP. | Arquimedes Canedo, Ben A. Abderazek, Masahiro Sowa |
| 2007 | SBAC-PAD | Queue Register File Optimization Algorithm for QueueCore Processor. | Arquimedes Canedo, Ben A. Abderazek, Masahiro Sowa |
| 2006 | ISPA | On the Design of a Dual-Execution Modes Processor: Architecture and Preliminary Evaluation. | Md. Musfiquzzaman Akanda, Ben A. Abderazek, Masahiro Sowa |
| 2005 | EUC | Modular Design Structure and High-Level Prototyping for Novel Embedded Processor Core. | Ben A. Abderazek, Sotaro Kawata, Tsutomu Yoshinaga, Masahiro Sowa |
| 2005 | EUC | An Efficient Dynamic Switching Mechanism (DSM) for Hybrid Processor Architecture. | Md. Musfiquzzaman Akanda, Ben A. Abderazek, Sotaro Kawata, Masahiro Sowa |
| 2003 | ISPA | On the Design of a Register Queue Based Processor Architecture (FaRM-rq). | Ben A. Abderazek, Soichi Shigeta, Tsutomu Yoshinaga, Masahiro Sowa |
| 1997 | PDPTA | Program Controlled Cache Memory on Parallel Computer. | Mitsuaki Nakasumi, Shusuke Okamoto, Masahiro Sowa |
| 1997 | PDPTA | Intruction Fetch Mechanism for PN-Superscalar. | Shusuke Okamoto, Masahiro Sowa |
| 1996 | PDPTA | Hybrid Processor Based on VLIW and PN-Superscalar. | Shusuke Okamoto, Masahiro Sowa |