| 2016 | ISCAS | A task allocation method for the DTTR scheme based on task scheduling of fault patterns. | Hiroshi Saito, Masashi Imai, Tomohiro Yoneda |
| 2015 | ICCD | A new encoding mechanism for low power inter-chip serial communication in asynchronous circuits. | Tomohiro Yoneda, Masashi Imai |
| 2014 | ISCAS | Multiple-clock multiple-edge-triggered multiple-bit flip-flops for two-phase handshaking asynchronous circuits. | Masashi Imai, Tomohiro Yoneda |
| 2012 | PRDC | Performance Modeling and Analysis of On-chip Networks for Real-Time Applications. | Masashi Imai, Tomohiro Yoneda |
| 2012 | PRDC | Multi-chip NoCs for Automotive Applications. | Tomohiro Yoneda, Masashi Imai, Naoya Onizawa, Atsushi Matsumoto, Takahiro Hanyu |
| 2010 | DSN | Pair and swap: An approach to graceful degradation for dependable chip multiprocessors. | Masashi Imai, Tomohide Nagai, Takashi Nanya |
| 2010 | PRDC | An Efficient Decision Unit for the Pair and Swap Methodology within Chip Multiprocessors. | James L. Weston, Masashi Imai, Tomohide Nagai, Takashi Nanya |
| 2009 | ICCD | N-way ring and square arbiters. | Masashi Imai, Tomohiro Yoneda, Takashi Nanya |
| 2009 | VLSID | Design and Implementation of Fine-Grain Power Gating with Ground Bounce Suppression. | Kimiyoshi Usami, Toshiaki Shirai, Tatsunori Hashida, Hiroki Masuda, Seidai Takeda, Mitsutaka Nakata, Naomi Seki, Hideharu Amano, Mitaro Namiki, Masashi Imai, Masaaki Kondo, Hiroshi Nakamura |
| 2007 | DATE | Interactive presentation: Task scheduling under performance constraints for reducing the energy consumption of the GALS multi-processor SoC. | Ryo Watanabe, Masaaki Kondo, Masashi Imai, Hiroshi Nakamura, Takashi Nanya |
| 2004 | ICCD | Asynchronous Scan-Latch controller for Low Area Overhead DFT. | Masayuki Tsukisaka, Masashi Imai, Takashi Nanya |
| 2004 | SRDS | Skewed Checkpointing for Tolerating Multi-Node Failures. | Hiroshi Nakamura, Takuro Hayashida, Masaaki Kondo, Yuya Tajima, Masashi Imai, Takashi Nanya |
| 2003 | ISCAS | Control signal sharing of asynchronous circuits using datapath delay information. | Hiroshi Saito, Euiseok Kim, Masashi Imai, Nattha Sretasereekul, Hiroshi Nakamura, Takashi Nanya |
| 2003 | ISCAS | A zero-time-overhead asynchronous four-phase controller. | Nattha Sretasereekul, Hiroshi Saito, Masashi Imai, Euiseok Kim, Metehan zcan, K. Thongnoo, Hiroshi Nakamura, Takashi Nanya |
| 1998 | ASPDAC | TITAC-2: An Asynchronous 32-bit Microprocessor. | Akihiro Takamura, Motokazu Ozawa, Izumi Fukasaku, Taro Fujii, Yoichiro Ueno, Masashi Imai, Masashi Kuwako, Takashi Nanya |
| 1997 | ICCD | TITAC-2: An asynchronous 32-bit microprocessor based on Scalable-Delay-Insensitive model. | Akihiro Takamura, Masashi Kuwako, Masashi Imai, Taro Fujii, Motokazu Ozawa, Izumi Fukasaku, Yoichiro Ueno, Takashi Nanya |