Masato Sakurai
Publication record assembled from the DBLP archive of ranked conferences.
Papers indexed
2
Venues
1
Active years
2012–2013
Best venue rank
B
Where they publish
Papers
2 indexed papers, newest first.
| Year | Venue | Title | Authors |
|---|---|---|---|
| 2013 | ASPDAC | Design of a clock jitter reduction circuit using gated phase blending between self-delayed clock edges. | Kiichi Niitsu, Naohiro Harigai, Daiki Hirabayashi, Daiki Oki, Masato Sakurai, Osamu Kobayashi, Takahiro J. Yamaguchi, Haruo Kobayashi |
| 2012 | ASPDAC | A reference-free on-chip timing jitter measurement circuit using self-referenced clock and a cascaded time difference amplifier in 65nm CMOS. | Kiichi Niitsu, Masato Sakurai, Naohiro Harigai, Daiki Hirabayashi, Takahiro J. Yamaguchi, Haruo Kobayashi |