Design of a clock jitter reduction circuit using gated phase blending between self-delayed clock edges.

Kiichi Niitsu, Naohiro Harigai, Daiki Hirabayashi, Daiki Oki, Masato Sakurai, Osamu Kobayashi, Takahiro J. Yamaguchi, Haruo Kobayashi

Browse the full ASPDAC paper archive.