Masaya Miyahara
Publication record assembled from the DBLP archive of ranked conferences.
Papers indexed
3
Venues
2
Active years
2011–2016
Best venue rank
C
Where they publish
Papers
3 indexed papers, newest first.
| Year | Venue | Title | Authors |
|---|---|---|---|
| 2016 | ISCAS | A 74.9 dB SNDR 1 MHz bandwidth 0.9 mW delta-sigma time-to-digital converter using charge pump and SAR ADC. | Anugerah Firdauzi, Zule Xu, Masaya Miyahara, Akira Matsuzawa |
| 2014 | ASPDAC | A dual-loop injection-locked PLL with all-digital background calibration system for on-chip clock generation. | Wei Deng, Ahmed Musa, Teerachot Siriburanon, Masaya Miyahara, Kenichi Okada, Akira Matsuzawa |
| 2011 | ISCAS | A 15.5 dB, wide signal swing, dynamic amplifier using a common-mode voltage detection technique. | James Lin, Masaya Miyahara, Akira Matsuzawa |