Matthew Grange
Publication record assembled from the DBLP archive of ranked conferences.
Papers indexed
1
Venues
1
Active years
2011–2011
Best venue rank
A
Where they publish
Papers
1 indexed papers, newest first.
| Year | Venue | Title | Authors |
|---|---|---|---|
| 2011 | ICCAD | Modeling the computational efficiency of 2-D and 3-D silicon processors for early-chip planning. | Matthew Grange, Axel Jantsch, Roshan Weerasekera, Dinesh Pamunuwa |