Matthew Naylor
Publication record assembled from the DBLP archive of ranked conferences.
Papers indexed
17
Venues
13
Active years
2005–2026
Best venue rank
A*
Where they publish
Papers
17 indexed papers, newest first.
| Year | Venue | Title | Authors |
|---|---|---|---|
| 2026 | ASPLOS | CHERI-SIMT: Implementing Capability Memory Protection in GPUs. | Matthew Naylor, Alexandre Joannou, A. Theodore Markettos, Paul Metzger, Simon W. Moore, Timothy M. Jones |
| 2025 | CCS | Deprivileging Low-Level GPU Drivers Efficiently with User-Space Processes and CHERI Compartments. | Paul Metzger, A. Theodore Markettos, Edward Tomasz Napierala, Matthew Naylor, Robert N. M. Watson, Timothy M. Jones |
| 2025 | ISCA | Adaptive CHERI Compartmentalization for Heterogeneous Accelerators. | Jianyi Cheng, A. Theodore Markettos, Alexandre Joannou, Paul Metzger, Matthew Naylor, Peter Rugg, Timothy M. Jones |
| 2024 | ICCD | Advanced Dynamic Scalarisation for RISC-V GPGPUs. | Matthew Naylor, Alexandre Joannou, A. Theodore Markettos, Paul Metzger, Simon W. Moore, Timothy M. Jones |
| 2021 | PDP | General hardware multicasting for fine-grained message-passing architectures. | Matthew Naylor, Simon W. Moore, David B. Thomas, Jonathan R. Beaumont, Shane T. Fleming, Mark Vousden, A. Theodore Markettos, Thomas Bytheway, Andrew D. Brown |
| 2020 | SP | Rigorous engineering for hardware security: Formal modelling and proof in the CHERI design and implementation process. | Kyndylan Nienhuis, Alexandre Joannou, Thomas Bauereiss, Anthony C. J. Fox, Michael Roe, Brian Campbell, Matthew Naylor, Robert M. Norton, Simon W. Moore, Peter G. Neumann, Ian Stark, Robert N. M. Watson, Peter Sewell |
| 2019 | FPL | Tinsel: A Manythread Overlay for FPGA Clusters. | Matthew Naylor, Simon W. Moore, David B. Thomas |
| 2016 | FMCAD | A consistency checker for memory subsystem traces. | Matthew Naylor, Simon W. Moore, Alan Mujumdar |
| 2015 | MEMOCODE | A generic synthesisable test bench. | Matthew Naylor, Simon W. Moore |
| 2014 | FPL | Rapid codesign of a soft vector processor and its compiler. | Matthew Naylor, Simon W. Moore |
| 2013 | FPL | A spiking neural network on a portable FPGA tablet. | Matthew Naylor, Paul James Fox, A. Theodore Markettos, Simon W. Moore |
| 2013 | FPL | Managing the FPGA memory wall: Custom computing or vector processing? | Matthew Naylor, Paul James Fox, A. Theodore Markettos, Simon W. Moore |
| 2010 | ICFP | The reduceron reconfigured. | Matthew Naylor, Colin Runciman |
| 2008 | HASKELL | Smallcheck and lazy smallcheck: automatic exhaustive testing for small values. | Colin Runciman, Matthew Naylor, Fredrik Lindblad |
| 2007 | HASKELL | A functional-logic library for wired. | Matthew Naylor, Emil Axelsson, Colin Runciman |
| 2007 | SCAM | Finding Inputs that Reach a Target Expression. | Matthew Naylor, Colin Runciman |
| 2005 | DICTA | Pixel Behaviour Metrics for Dynamic Background Modelling with the Projected Difference Pattern Method. | Peter Pakulski, Karl Sammut, Fangpo He, Matthew Naylor |