Maurice Keller
Publication record assembled from the DBLP archive of ranked conferences.
Papers indexed
1
Venues
1
Active years
2005–2005
Best venue rank
B
Where they publish
Papers
1 indexed papers, newest first.
| Year | Venue | Title | Authors |
|---|---|---|---|
| 2005 | FPL | FPGA Implementation of a GF(2 | Maurice Keller, Tim Kerins, William P. Marnane |