Michael S. Schlansker
Publication record assembled from the DBLP archive of ranked conferences.
Papers indexed
18
Venues
7
Active years
1973–2007
Best venue rank
A*
Where they publish
Papers
18 indexed papers, newest first.
| Year | Venue | Title | Authors |
|---|---|---|---|
| 2007 | SC | High-performance ethernet-based communications for future multi-core processors. | Michael S. Schlansker, Nagabhushan Chitlur, Erwin Oertli, Paul M. Stillwell Jr., Linda Rankin, Dennis Bradford, Richard J. Carter, Jayaram Mudigonda, Nathan L. Binkert, Norman P. Jouppi |
| 2006 | MICRO | Exploiting Fine-Grained Data Parallelism with Chip Multiprocessors and Fast Barriers. | Jack Sampson, Rubn Gonzlez, Jean-Francois Collard, Norman P. Jouppi, Michael S. Schlansker, Brad Calder |
| 2003 | MICRO | In Memory of Bob Rau. | Michael S. Schlansker |
| 2001 | CASES | ShiftQ: a bufferred interconnect for custom loop accelerators. | Shail Aditya, Michael S. Schlansker |
| 2000 | HiPC | Embedded Computing: New Directions in Architecture and Automation. | B. Ramakrishna Rau, Michael S. Schlansker |
| 1999 | PLDI | Control CPR: A Branch Height Reduction Optimization for EPIC Architectures. | Michael S. Schlansker, Scott A. Mahlke, Richard Johnson |
| 1996 | MICRO | Profile-driven Instruction Level Parallel Scheduling with Application to Super Blocks. | Chandra Chekuri, Richard Johnson, Rajeev Motwani, B. Natarajan, B. Ramakrishna Rau, Michael S. Schlansker |
| 1996 | MICRO | Global Predicate Analysis and Its Application to Register Allocation. | David M. Gillies, Roy Dz-Ching Ju, Richard Johnson, Michael S. Schlansker |
| 1996 | MICRO | Analysis Techniques for Predicated Code. | Richard Johnson, Michael S. Schlansker |
| 1995 | MICRO | Spill-free parallel scheduling of basic blocks. | B. Natarajan, Michael S. Schlansker |
| 1995 | MICRO | Critical path reduction for scalar programs. | Michael S. Schlansker, Vinod Kathail |
| 1994 | MICRO | Height reduction of control recurrences for ILP processors. | Michael S. Schlansker, Vinod Kathail, Sadun Anik |
| 1992 | ASPLOS | Sentinel Scheduling for VLIW and Superscalar Processors. | Scott A. Mahlke, William Y. Chen, Wen-mei W. Hwu, B. Ramakrishna Rau, Michael S. Schlansker |
| 1992 | MICRO | Code generation schema for modulo scheduled loops. | B. Ramakrishna Rau, Michael S. Schlansker, Parthasarathy P. Tirumalai |
| 1992 | PLDI | Register Allocation for Software Pipelined Loops. | B. Ramakrishna Rau, Meng Lee, Parthasarathy P. Tirumalai, Michael S. Schlansker |
| 1990 | SC | Parallelization of loops with exits on pipelined architectures. | Parthasarathy P. Tirumalai, Meng Lee, Michael S. Schlansker |
| 1989 | ICPP | The Cydram 5 Stride-Insensitive Memory System. | B. Ramakrishna Rau, Michael S. Schlansker, David W. L. Yen |
| 1973 | MICRO | A microprogramming language for the B-1726. | David J. DeWitt, Michael S. Schlansker, Daniel E. Atkins |