Michael Scheppler
Publication record assembled from the DBLP archive of ranked conferences.
Papers indexed
3
Venues
3
Active years
2005–2006
Best venue rank
A
Where they publish
Papers
3 indexed papers, newest first.
| Year | Venue | Title | Authors |
|---|---|---|---|
| 2006 | DATE | Automated conversion from a LUT-based FPGA to a LUT-based MPGA with fast turnaround time. | Francisco-Javier Veredas, Michael Scheppler, Hans-Jrg Pfleiderer |
| 2006 | ISCAS | LUT-based MPGAs for fast turnaround time conversion flow. | Francisco-Javier Veredas, Michael Scheppler, Bumei Zhai, Hans-Jrg Pfleiderer |
| 2005 | FPL | Custom Implementation of the Coarse-Grained Reconfigurable ADRES Architecture for Multimedia Purposes. | Francisco-Javier Veredas, Michael Scheppler, Will Moffat, Bingfeng Mei |