Michael Shebanow
Publication record assembled from the DBLP archive of ranked conferences.
Papers indexed
9
Venues
3
Active years
1985–2013
Best venue rank
A*
Where they publish
Papers
9 indexed papers, newest first.
| Year | Venue | Title | Authors |
|---|---|---|---|
| 2013 | ISPASS | Peta Thread Computing [Keynote I]. | Michael Shebanow |
| 2011 | MICRO | Improving GPU performance via large warps and two-level warp scheduling. | Veynu Narasiman, Michael Shebanow, Chang Joo Lee, Rustam Miftakhutdinov, Onur Mutlu, Yale N. Patt |
| 1995 | ISCA | Implementation Trade-Offs in Using a Restricted Data Flow Architecture in a High Performance RISC Microprocessor. | Mike Simone, A. Essen, A. Ike, A. Krishnamoorthy, Tak Maruyama, Niteen Patkar, M. Ramaswami, Michael Shebanow, V. Thirumalaiswamy, DeForest Tovey |
| 1991 | ISCA | Single Instruction Stream Parallelism is Greater Than Two. | Michael Butler, Tse-Yu Yeh, Yale N. Patt, Mitch Alsup, Hunter Scales, Michael Shebanow |
| 1988 | MICRO | Hardware support for large atomic units in dynamically scheduled machines. | Stephen W. Melvin, Michael Shebanow, Yale N. Patt |
| 1987 | MICRO | On tuning the microarchitecture of an HPS implementation of the VAX. | James E. Wilson, Stephen W. Melvin, Michael Shebanow, Wen-mei W. Hwu, Yale N. Patt |
| 1986 | MICRO | Run-time generation of HPS microinstructions from a VAX instruction stream. | Yale N. Patt, Stephen W. Melvin, Wen-mei W. Hwu, Michael Shebanow, Chein Chen |
| 1985 | MICRO | HPS, a new microarchitecture: rationale and introduction. | Yale N. Patt, Wen-mei W. Hwu, Michael Shebanow |
| 1985 | MICRO | Critical issues regarding HPS, a high performance microarchitecture. | Yale N. Patt, Stephen W. Melvin, Wen-mei W. Hwu, Michael Shebanow |