| 2024 | ISCAS | ALPACA: An Accelerator Chip for Nested Loop Programs. | Dominik Walter, Marcel Brand, Christian Heidorn, Michael Witterauf, Frank Hannig, Jrgen Teich |
| 2021 | SAC | Aarith: an arbitrary precision number library. | Oliver Keszcze, Marcel Brand, Michael Witterauf, Christian Heidorn, Jrgen Teich |
| 2020 | MEMOCODE | Real-time Scheduling of I/O Transfers for Massively Parallel Processor Arrays. | Dominik Walter, Michael Witterauf, Jrgen Teich |
| 2019 | MEMOCODE | Polyhedral fragments: an efficient representation for symbolically generating code for processor arrays. | Michael Witterauf, Frank Hannig, Jrgen Teich |
| 2018 | MEMOCODE | Run-time Requirement Enforcement for Loop Programs on Processor Arrays. | Michael Witterauf, Jrgen Teich |
| 2017 | RSP | Constructing fast and cycle-accurate simulators for configurable accelerators using C++ templates. | Michael Witterauf, Frank Hannig, Jrgen Teich |
| 2015 | MEMOCODE | Symbolic loop parallelization for balancing I/O and memory accesses on processor arrays. | Alexandru Tanase, Michael Witterauf, Jrgen Teich, Frank Hannig |
| 2014 | MEMOCODE | Symbolic inner loop parallelisation for massively parallel processor arrays. | Alexandru Tanase, Michael Witterauf, Jrgen Teich, Frank Hannig |