Michinobu Nakao
Publication record assembled from the DBLP archive of ranked conferences.
Papers indexed
4
Venues
1
Active years
1999–2008
Best venue rank
A
Where they publish
Papers
4 indexed papers, newest first.
| Year | Venue | Title | Authors |
|---|---|---|---|
| 2008 | ITC | Hardware Overhead Reduction for Memory BIST. | Masayuki Arai, Kazuhiko Iwasaki, Michinobu Nakao, Iwao Suzuki |
| 2002 | ITC | Application of High-Quality Built-In Test to Industrial Designs. | Kazumi Hatayama, Michinobu Nakao, Yoshikazu Kiyoshige, Koichiro Natsume, Yasuo Sato, Takaharu Nagumo |
| 2000 | ITC | A BIST approach for very deep sub-micron (VDSM) defects. | Yasuo Sato, Toyohito Ikeya, Michinobu Nakao, Takaharu Nagumo |
| 1999 | ITC | Low overhead test point insertion for scan-based BIST. | Michinobu Nakao, Seiji Kobayashi, Kazumi Hatayama, Kazuhiko Iijima, Seiji Terada |