Mike Tien-Chien Lee
Publication record assembled from the DBLP archive of ranked conferences.
Papers indexed
11
Venues
6
Active years
1995–1998
Best venue rank
A*
Where they publish
Papers
11 indexed papers, newest first.
| Year | Venue | Title | Authors |
|---|---|---|---|
| 1998 | DATE | Functional Scan Chain Testing. | Douglas Chang, Kwang-Ting Cheng, Malgorzata Marek-Sadowska, Mike Tien-Chien Lee |
| 1997 | ASPDAC | On the control-subroutine implementation of subprogram synthesis. | Cheng-Tsung Hwang, Hsiao-Chien Weng, Yu-Chin Hsu, Mike Tien-Chien Lee |
| 1997 | DAC | A Test Synthesis Approach to Reducing BALLAST DFT Overhead. | Douglas Chang, Mike Tien-Chien Lee, Malgorzata Marek-Sadowska, Takashi Aikyo, Kwang-Ting Cheng |
| 1996 | DAC | Using Register-Transfer Paths in Code Generation for Heterogeneous Memory-Register Architectures. | Guido Araujo, Sharad Malik, Mike Tien-Chien Lee |
| 1996 | DAC | Domain-Specific High-Level Modeling and Synthesis for ATM Switch Design Using VHDL. | Mike Tien-Chien Lee, Yu-Chin Hsu, Ben Chen, Masahiro Fujita |
| 1996 | DAC | Test Point Insertion: Scan Paths through Combinational Logic. | Chih-Chang Lin, Malgorzata Marek-Sadowska, Kwang-Ting Cheng, Mike Tien-Chien Lee |
| 1996 | DATE | Sequential Permissible Functions and their Application to Circuit Optimization. | Chih-Chang Lin, Malgorzata Marek-Sadowska, Kuang-Chien Chen, Mike Tien-Chien Lee |
| 1996 | ISLPED | A novel methodology for transistor-level power estimation. | Shi-Yu Huang, Kwang-Ting Cheng, Kuang-Chien Chen, Mike Tien-Chien Lee |
| 1996 | VLSID | Instruction Level Power Analysis and Optimization of Software. | Vivek Tiwari, Sharad Malik, Andrew Wolfe, Mike Tien-Chien Lee |
| 1995 | ASPDAC | Power analysis of a 32-bit embedded microcontroller. | Vivek Tiwari, Mike Tien-Chien Lee |
| 1995 | ICCAD | Cost-free scan: a low-overhead scan path design methodology. | Chih-Chang Lin, Mike Tien-Chien Lee, Malgorzata Marek-Sadowska, Kuang-Chien Chen |