Min-Han Hsieh
Publication record assembled from the DBLP archive of ranked conferences.
Papers indexed
7
Venues
1
Active years
2011–2015
Best venue rank
C
Where they publish
Papers
7 indexed papers, newest first.
| Year | Venue | Title | Authors |
|---|---|---|---|
| 2015 | ISCAS | A 8.1/5.4/2.7/1.62 Gb/s receiver for DisplayPort Version 1.3 with automatic bit-rate tracking scheme. | Ai Chien, Shuo-Hong Hung, Kuan-I Wu, Chang-Yi Liu, Min-Han Hsieh, Charlie Chung-Ping Chen |
| 2015 | ISCAS | A 160MHz-to-2GHz low jitter fast lock all-digital DLL with phase tracking technique. | Shuo-Hong Hung, Wei-Hao Kao, Kuan-I Wu, Yi-Wei Huang, Min-Han Hsieh, Charlie Chung-Ping Chen |
| 2013 | ISCAS | A 10-bit current-steering DAC for HomePlug AV2 powerline communication system in 90nm CMOS. | Wei-Sheng Cheng, Min-Han Hsieh, Shuo-Hong Hung, Szu-Yao Hung, Charlie Chung-Ping Chen |
| 2013 | ISCAS | A 52 dBc MTPR line driver for powerline communication HomePlug AV standard in 0.18-μm CMOS technology. | Pang-Kai Liu, Szu-Yao Hung, Chang-Yi Liu, Min-Han Hsieh, Charlie Chung-Ping Chen |
| 2012 | ISCAS | A 2 - 8 GHz multi-phase distributed DLL using phase insertion in 90 nm. | Min-Han Hsieh, Bing-Feng Lin, Yu-Shun Wang, Hao-Huei Chang, Charlie Chung-Ping Chen |
| 2011 | ISCAS | A 1.2V 6.4GHz 181ps 64-bit CD domino adder with DLL measurement technique. | Yu-Shun Wang, Min-Han Hsieh, Chia-Ming Liu, Yi-Chi Wu, Bing-Feng Lin, Hsien-Chen Chiu, Charlie Chung-Ping Chen |
| 2011 | ISCAS | A 12 Gb/s chip-to-chip AC coupled transceiver. | Yu-Shun Wang, Min-Han Hsieh, Yi-Chi Wu, Chia-Ming Liu, Hsien-Chen Chiu, Bing-Feng Lin, Charlie Chung-Ping Chen |