Min-Hsiu Tsai
Publication record assembled from the DBLP archive of ranked conferences.
Papers indexed
5
Venues
3
Active years
2008–2016
Best venue rank
A
Where they publish
Papers
5 indexed papers, newest first.
| Year | Venue | Title | Authors |
|---|---|---|---|
| 2016 | ICCAD | Statistical methodology to identify optimal placement of on-chip process monitors for predicting fmax. | Szu-Pang Mu, Wen-Hsiang Chang, Mango C.-T. Chao, Yi-Ming Wang, Ming-Tung Chang, Min-Hsiu Tsai |
| 2011 | ITC | Test clock domain optimization for peak power supply noise reduction during scan. | Jen-Yang Wen, Yu-Chuan Huang, Min-Hong Tsai, Kuan-Yu Liao, James Chien-Mo Li, Ming-Tung Chang, Min-Hsiu Tsai, Chih-Mou Tseng, Hung-Chun Li |
| 2010 | DATE | TSV redundancy: Architecture and design issues in 3D IC. | Ang-Chih Hsieh, TingTing Hwang, Ming-Tung Chang, Min-Hsiu Tsai, Chih-Mou Tseng, Hung-Chun Li |
| 2009 | ICCAD | BIST design optimization for large-scale embedded memory cores. | Tzuo-Fan Chien, Wen-Chi Chao, James Chien-Mo Li, Yao-Wen Chang, Kuan-Yu Liao, Ming-Tung Chang, Min-Hsiu Tsai, Chih-Mou Tseng |
| 2008 | ITC | Capture and Shift Toggle Reduction (CASTR) ATPG to Minimize Peak Power Supply Noise. | Hsiu-Ting Lin, Jen-Yang Wen, James Li, Ming-Tung Chang, Min-Hsiu Tsai, Sheng-Chih Huang, Chili-Mou Tseng |