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Ming-che Lai

Publication record assembled from the DBLP archive of ranked conferences.

Papers indexed

9

Venues

6

Active years

2005–2022

Best venue rank

A*

Where they publish

Papers

9 indexed papers, newest first.

YearVenueTitleAuthors
2022NPCSpacKV: A Pmem-Aware Key-Value Separation Store Based on LSM-Tree.Xuran Ge, Ming-che Lai, Yang Liu, Lizhou Wu, Zhutao Zhuang, Yang Ou, Zhiguang Chen, Nong Xiao
2009ICCADAn accurate and efficient performance analysis approach based on queuing model for network on chip.Ming-che Lai, Lei Gao, Nong Xiao, Zhiying Wang
2009ICPADSAn Improved Parallel Access Technology on Routing Table for Threaded BGP.Lei Gao, Ming-che Lai, Zhenghu Gong
2008CISISMemory System Design for a Multi-core Processor.Jianjun Guo, Ming-che Lai, Zhengyuan Pang, Libo Huang, Fangyuan Chen, Kui Dai, Zhiying Wang
2008CISISEscaping from Blocking: A Dynamic Virtual Channel for Pipelined Routers.Ming-che Lai, Lei Gao, Wei Shi, Zhiying Wang
2008CISISUsing an Automated Approach to Explore and Design a High-Efficiency Processor Element for the Multimedia Domain.Ming-che Lai, Jianjun Guo, Zhuxi Zhang, Zhiying Wang
2008DACA dynamically-allocated virtual channel architecture with congestion awareness for on-chip routers.Ming-che Lai, Zhiying Wang, Lei Gao, Hongyi Lu, Kui Dai
2008SACHierarchical memory system design for a heterogeneous multi-core processor.Jianjun Guo, Ming-che Lai, Zhengyuan Pang, Libo Huang, Fangyuan Chen, Kui Dai, Zhiying Wang
2005ICPADSDesign of a Configurable Embedded Processor Architecture for DSP Functions.Hong Yue, Ming-che Lai, Kui Dai, Zhiying Wang