Minhan Chen
Publication record assembled from the DBLP archive of ranked conferences.
Papers indexed
2
Venues
1
Active years
2022–2024
Best venue rank
C
Where they publish
Papers
2 indexed papers, newest first.
| Year | Venue | Title | Authors |
|---|---|---|---|
| 2024 | ISCAS | A Reduced-Fractional-Spur DPLL Based on Cyclic Single-Delay-Pair Vernier TDC. | Ping Lu, Minhan Chen, Shaishav Desai |
| 2022 | ISCAS | A Low-Ripple Resistor-Less Hybrid Loop Filter based PLL in 3nm FinFET. | Ping Lu, Charlie Boecker, Bupesh Pandita, Minhan Chen, Sheethal Nayak |