Mitsuyasu Ohta
Publication record assembled from the DBLP archive of ranked conferences.
Papers indexed
3
Venues
2
Active years
1995–2001
Best venue rank
B
Where they publish
Papers
3 indexed papers, newest first.
| Year | Venue | Title | Authors |
|---|---|---|---|
| 2001 | ASPDAC | Design for testability strategies using full/partial scan designs and test point insertions to reduce test application times. | Toshinori Hosokawa, Masayoshi Yoshimura, Mitsuyasu Ohta |
| 2000 | ITC | On validating data hold times for flip-flops in sequential circuits. | Sudhakar M. Reddy, Irith Pomeranz, Seiji Kajihara, Atsushi Murakami, Sadami Takeoka, Mitsuyasu Ohta |
| 1995 | ASPDAC | Design for testability using register-transfer level partial scan selection. | Akira Motohara, Sadami Takeoka, Toshinori Hosokawa, Mitsuyasu Ohta, Yuji Takai, Michihiro Matsumoto, Michiaki Muraoka |