| 2012 | DATE | A resilient architecture for low latency communication in shared-L1 processor clusters. | Mohammad Reza Kakoee, Igor Loi, Luca Benini |
| 2011 | DATE | ReliNoC: A reliable network for priority-based on-chip communication. | Mohammad Reza Kakoee, Valeria Bertacco, Luca Benini |
| 2011 | DATE | A fully-synthesizable single-cycle interconnection network for Shared-L1 processor clusters. | Abbas Rahimi, Igor Loi, Mohammad Reza Kakoee, Luca Benini |
| 2010 | ISLPED | Automatic synthesis of near-threshold circuits with fine-grained performance tunability. | Mohammad Reza Kakoee, Ashoka Visweswara Sathanur, Antonio Pullini, Jos Huisken, Luca Benini |
| 2008 | DATE | De Bruijn Graph as a Low Latency Scalable Architecture for Energy Efficient Massive NoCs. | Mohammad Hosseinabady, Mohammad Reza Kakoee, Jimson Mathew, Dhiraj K. Pradhan |
| 2008 | DSD | Generating RTL Synthesizable Code from Behavioral Testbenches for Hardware-Accelerated Verification. | Mohammad Reza Kakoee, Mohammad Riazati, Siamak Mohammadi |
| 2007 | AICCSA | Improving Robustness of Real-Time Operating Systems (RTOS) Services Related to Soft-Errors. | Mohammad Hossein Neishaburi, Masoud Daneshtalab, Mohammad Reza Kakoee, Saeed Safari |
| 2007 | DDECS | A HW/SW Architecture to Reduce the Effects of Soft-Errors in Real-Time Operating System Services. | Mohammad Hossein Neishaburi, Mohammad Reza Kakoee, Masoud Daneshtalab, Saeed Safari, Zainalabedin Navabi |
| 2007 | DSD | On-Chip Verification of NoCs Using Assertion Processors. | Mohammad Reza Kakoee, Mohammad Hossein Neishaburi, Masoud Daneshtalab, Saeed Safari, Zainalabedin Navabi |
| 2007 | DSD | Functional Test-Case Generation by a Control Transaction Graph for TLM Verification. | Mohammad Reza Kakoee, Mohammad Hossein Neishaburi, Siamak Mohammadi |
| 2007 | ISCAS | A New Approach for Design and Verification of Transaction Level Models. | Mohammad Reza Kakoee, Hamid Shojaei, Hassan Ghasemzadeh, Marjan Sirjani, Zainalabedin Navabi |