Mursina Khatun
Publication record assembled from the DBLP archive of ranked conferences.
Papers indexed
2
Venues
1
Active years
2024–2024
Best venue rank
C
Where they publish
Papers
2 indexed papers, newest first.
| Year | Venue | Title | Authors |
|---|---|---|---|
| 2024 | ISCAS | A 0.2 pJ/bit, Energy-Efficient, Half-Rate Hybrid Circuit Topology at 6-Gb/s in 1.2V, 65 nm CMOS. | Prema Kumar Govindaswamy, Mursina Khatun, Vijay Shankar Pasupureddi |
| 2024 | ISCAS | A 2 | Prema Kumar Govindaswamy, Mursina Khatun, Vijay Shankar Pasupureddi |